Computer Architecture Seminar

Course Code: B62009H

Course Name: Computer Architecture Seminar

Course Properties: professional basic course

Periods &Credits: 40/2.0

Level: Undergraduate

Pre-requisite: Digital Logic Circuit, Principles of Computer Organization

Instructors: Dr. Wenxiang Wang

Course Description

The purpose of this seminar is to deepen students' understanding of computer organization and architecture. Students will master the computer design process and computer control theory. Then their operational ability of computer systems synthesis, the capabilities of system debug and the ability to test system failure and exclude failure will be improved. Students are required to design a small computer hardware system by using hardware programming language (Verilog) with FPGA based on their understanding of computer architecture. Students are also required to design and define the basic program instructions and to write assembler with defined instructions. A minicomputer system will be designed that could recognize the command and implement functions in a FPGA experimental board.

Topics and Schedule

This course mainly covers the organizational structure and working principle of the computer, which contains organizational characteristics and working principle of the computer functional components respectively. Then students will establish the concept of the computer machine and understand the computer work process. Thus they would acquire complete knowledge about the computer system. Hands-on experiments and answering questions on the class are taken as the main teaching form which will be supplemented by a number of classroom teachings. Concrete contents include:

Discussion 1            Data operation: Fixed point addition implementation

Discussion 2            Data operation: Fixed point multiplication implementation

Discussion 3            Register files implementation

Discussion 4            ALU module implementation

Discussion 5            Memory implementation

Discussion 6            Single cycle CPU implementation

Discussion 7            More cycles CPU implementation

Course design         static 5-stage pipeline CPU implementation


Computer Architecture Experiment Guidebook (self edit version)


Computer Architecture course notes